Microcoded ATM System

Overview

Synthesized and verified a hardware-based ATM controller on an Intel FPGA using IEEE standard VHDL, shifting from traditional rigid hardwired FSMs to a flexible microcoded control architecture with decoupled control and data paths.

Key Features

• ◆Microprogrammed Control Unit with ROM-based microcode store for complex state transitions (IDLE, CHECK, OPERATE, DONE)
• ◆Parallel hardware PIN validation accelerator inside the Data Plane for zero-latency verification
• ◆Synchronous Block RAM memory interface for secure user database lookups, balance queries, and fee calculations
• ◆Modular structural VHDL design decoupling control path logic from arithmetic/memory data path
• ◆Self-checking ModelSim testbench with automated clock stimuli and expected-output assertions

Skills